Ultra Low Power High Speed MAC Unit Using LP-HS Logic in CMOS Technologies

A modified approach for constant delay logic style is developed in this paper to provide improved power and delay named LP-HS logic. Constant delay logic style is examined against the LP-HS logic, by analysis through simulation. It is shown that the proposed LP-HS logic has low power, delay and power delay product over the existing constant delay logic style. Multiplier accumulator unit is one of the important applications in DSP. In this paper the comparison of MAC using both constant delay logic style as well as LPHS logic have been done. The simulation results shows that MAC using LP-HS logic is better in terms of power, delay and power delay product when compared to constant delay logic style. The simulations were done using HSPICE tool in 45nm, 32nm, 22nm and 16nm CMOS technologies and performance parameters of power, delay and power delay product were compared.